Non-volatile memory cells include a floating gate in which electric charge may be injected. As implied by the name, the floating gate electrically “floats” with regard to other structures in the cell such that the injected charge is retained even if the memory cell is powered down. In a classic non-volatile memory cells, two separate polysilicon layers are required. A first polysilicon layer forms the floating gate. A second overlaying polysilicon layer forms a control gate that is used to program the floating gate. Because CMOS semiconductor manufacturing processes provide only a single polysilicon layer, “single-poly” non-volatile memory cells have been developed in which the control gate is formed as a buried diffusion region.
Although conventional single-poly non-volatile memory cells are compatible with CMOS manufacturing processes, the buried diffusion area occupies die area and thus decreases device density, thereby increasing manufacturing costs. Moreover, the buried diffusion region is prone to junction breakdown. To increase density, single-poly non-volatile memory cells have been developed in which the control gate is implemented as a trench metal-insulator-metal (MIM) capacitor. However, forming a trench MIM capacitor demands extra processing steps and thus also increases costs.
Accordingly, there is a need in the art for improved non-volatile memory cells.